The invention lies in the field of semiconductor technology. More specifically, the present invention relates to a method for fabricating a semiconductor insulation layer.
In state of the art technology, insulation layers on substrates in semiconductor components are fabricated by an extensive array of different technologies. Two examples thereof are the LOCOS technology and the STI (Shallow Trench Isolation) technology. In this context, the term substrate should be understood to mean any support, and not merely a wafer substrate. A substrate, as meant herein, may therefore be a wafer substrate, an epitaxial structure, a well in a wafer substrate, a circuit in a wafer substrate, etc.
A disadvantageous fact that has come to light in the case of the prior art approaches noted above is that they require a high process outlay and the insulation layer is frequently susceptible to shear tension and stress within itself and with respect to the substrate; the latter applies in particular to LOCOS technology.
It is accordingly an object of the invention to provide a method for fabricating a semiconductor insulation layer, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes it possible to create stress-free, stable insulation with a comparatively low process outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a semiconductor insulation layer, which comprises the following steps:
providing a semiconductor substrate;
forming (region-by-region or whole-area layer formation) an insulation layer on the semiconductor substrate; selectively implanting impurity ions into a predetermined zone of the insulation layer; and
selectively etching the insulation layer and patterning the insulation layer in correspondence with the predetermined zone selectively implanted impurity ions.
By contrast with the prior art approaches, the method according to the invention has the advantage that it enables an insulation structure without tensions in a simple and cost-effective process.
The basic premise on which the present invention is founded includes the patterning of the insulation layer in accordance with zones of selectively implanted impurity ions by means of selective etching of an insulation layer on a semiconductor substrate.
In accordance with an added feature of the invention, the substrate is a silicon semiconductor substrate and the insulation layer formed on the substrate is a silicon dioxide layer. Preferably, the insulation layer is a thermal oxide layer. The silicon semiconductor substrate is the most usual case. It should be noted, however, that the present invention is in no way restricted to this, rather other semiconductor materials can readily be used. Thermal oxide layers exhibit particularly good connection to the substrate.
In accordance with an additional feature of the invention, a layer of thermal oxide is formed on the semiconductor substrate and a layer of non-thermal oxide on the layer of thermal oxide. In a preferred embodiment, the non-thermal oxide is a TEOS or LTO (low temperature oxide), applied over the layer of thermal oxide. Such an oxide not only provides a good connection to the substrate but can also be applied with high deposition rates.
In accordance with another feature of the invention, the selective implantation is carried out using at least one mask, in particular a photoresist mask. This is the customary way of patterning in the case of wet and dry etching, but it goes without saying that other masks, such as e.g. nitride masks, etc., can also be used.
In accordance with a further feature of the invention, the selective implantation is carried out at different angles and/or energies and/or doses. The etching zones can be accurately patterned in this way.
In accordance with a further preferred development, the selective implantation and etching are carried out in such a way that the insulation layer in the implanted zones is removed by the etching. This should be understood as a positive process and constitutes the preferred case in which the implanted ions weaken the bond structure.
In accordance with a further preferred development, the selective implantation and etching are carried out in such a way that the insulation layer in the implanted zones is not removed by the etching. This should be understood as a negative process and is somewhat more complicated in terms of process engineering since, as a rule, an additional high-temperature process is necessary in order to bind the incorporated ions stably into the bond structure.
In accordance with a further preferred development, the selective implantation and etching are carried out in such a way that a contact region is formed, which is continuous through the insulation layer as far as the semiconductor substrate and whose sidewalls are designed to be stepped, for example.
In accordance with again an added feature of the invention, at least one element selected from the group consisting of Ar, N, O, B, As, and P, is implanted and a concentration of the impurities defines an etching rate in the respective zone. This means, as a rule, that a high impurity concentration is equivalent to a high local etching rate.
With the above and other objects in view there is further provided, in accordance with the invention, a method of fabricating a semiconductor component with the semiconductor insulation layer according to the foregoing summary. The method comprises the following steps:
providing a semiconductor substrate;
forming a whole-area insulation layer on the semiconductor substrate with a predetermined thickness;
forming a first mask on the insulation layer and defining a first predetermined zone;
selectively implanting impurity ions into the first predetermined zone of the insulation layer defined by the first mask, and thereby selecting an implantation profile in accordance with an etching zone situated on the surface and having a smaller thickness than the predetermined thickness of the insulation layer;
selectively etching the insulation layer in the first predetermined zone in accordance with the mask;
forming a second mask on the semiconductor substrate and defining a second predetermined zone of the insulation layer;
selectively implanting impurity ions into the second predetermined zone of the insulation layer, and selecting an implantation profile in accordance with an etching zone having the same thickness as the thickness of the insulation layer;
selectively etching the insulation layer in the first predetermined zone and uncovering the semiconductor substrate;
forming a whole-area conductive layer on the structure formed in the selectively etching; and polishing the conductive layer substantially to the thickness of the insulation layer.
In other words, the novel method for fabricating the semiconductor component that contains the semiconductor insulation layer as defined above provides the following patterning of the insulation layer applied to the semiconductor substrate: formation of a first mask on the semiconductor substrate; selective implantation of impurity ions into a first predetermined zone in accordance with the first mask of the insulation layer, the implantation profile being selected in accordance with an etching zone situated on the surface and having a smaller thickness than the thickness of the insulation layer; selective etching of the insulation layer in the first predetermined zone in accordance with the mask; formation of a second mask on the semiconductor substrate; selective implantation of impurity ions into a second predetermined zone in accordance with the second mask of the insulation layer, the implantation profile being selected in accordance with an etching zone having the same thickness as the thickness of the insulation layer; selective etching of the insulation layer in the first predetermined zone in accordance with the mask for the purpose of uncovering the semiconductor substrate; whole-area application of a conductive layer to the resulting structure; and polishing, in particular chemical mechanical polishing, of the conductive layer to essentially the thickness of the insulation layer.
This procedure creates contact regions, thick insulation regions and thin insulation regions with, incorporated into the insulation layer, planarized interconnects of the conductive layer, which are connected to the substrate via the contact regions.
In accordance with a further preferred development, the conductive layer is patterned.
In accordance with a further preferred development, a field-effect transistor is formed with a channel well zone in the second predetermined zone in accordance with the second mask, a superior gate insulator layer and source and drain zones in the adjoining region of the semiconductor substrate.
In accordance with a further preferred development, the following are carried out: formation of the first mask on the semiconductor substrate in accordance with a dumbbell-shaped zone; formation of the second mask on the semiconductor substrate in accordance with a respective zone in the dumbbell plates of the dumbbell-shaped zone in accordance with the first mask; and formation of a respective field-effect transistor with a channel well zone in the respective zone in accordance with the second mask, a superior gate insulator layer and source and drain zones in the adjoining region of the semiconductor substrate; the conductive layer, which runs across the dumbbell web, connecting the two gate terminals of the field-effect transistors. In this way, it is possible to form a simple field-effect transistor inverter structure with a common gate terminal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor insulation layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.